The disclosed device generally relates to clock synchronization devices for removing skews of clock signals, and more particularly, to a clock synchronization device which can reduce initial synchronization time by using a feed-forward type duty corrector circuit.
Referring to FIG. 1 a block diagram illustrating a conventional clock synchronization device is disclosed, and a hierarchical phase locking delay (xe2x80x98HPLDxe2x80x99) circuit is described. The conventional clock synchronization device includes a clock buffer 1, a coarse control unit 2, a coarse delay line 3, a fine control unit 4, a fine delay line 5 and a duty corrector 6.
The clock buffer 1 transmits external clock signals (ECLK) into an internal circuitry. The coarse delay line 3, including several unit coarse delay cells connected in series, delays the clock signals (BCLK) transmitted from the clock buffer 1 for a predetermined time and then outputs coarse delay clock signals (CCLK). The coarse control unit 2 adjusts the delay time of the coarse delay line 3 via enable signals EN.
The fine delay line 5 includes several unit fine delay cells connected in series. The fine delay line 5 delays coarse delay clock signals CCLK outputted from the coarse delay line 3 for a predetermined time and then outputs fine clock signals FCLK. The delay time of unit fine delay cells is smaller than that of unit coarse delay cells in the coarse delay line 3, thereby providing a more finely delayed signal. The fine control unit 4 adjusts the delay time of the fine delay line 5 according to control signals (CON).
The duty corrector 6 adjusts the duty cycle of the fine delay clock signals FCLK outputted from the fine delay line 5, and then outputs internal clock signals ICLK. A feedback type duty corrector 6 uses the principle that the whole current difference between the high time interval and the low time interval of the clock signal is xe2x80x980xe2x80x99 in the case of clock signals maintaining a duty-ratio of 50%.
FIG. 2 is a more detailed block diagram illustrating the duty corrector 6 of the conventional clock synchronization device described above. The duty corrector 6 includes a charge pump 7, a capacitor C, an output amplifier 8 and a buffer 9.
When an internal clock signal ICLK outputted from the duty corrector 6 is fed back to the charge pump 7, an output current charge from the charge pump 7 is stored in the capacitor C as a current valve according to the internal clock signal ICLK. The current value stored in the capacitor C is converted into a voltage value, and the voltage value is fed back to the output amplifier 8. As a result, output signals of the output amplifier 8 adjust the duty-ratio of the internal clock signals ICLK to 50% by transforming the common mode level of signals in the buffer 9 having small swing.
However, the duty corrector 6 used in the conventional clock synchronization device has long initial phase synchronization time due to the feed-back technique. In addition, according to the conventional clock synchronization device described above, jitter is not compensated for, DC currents are increased and information on the duty ratio is stored in the capacitor C as an analog value. As a result, the hold time is limited when the clock synchronization device is instantly stopped.
A clock synchronization device is provided which includes: a coarse delay line; a coarse control unit; a clock interface; a fine delay line; a fine control unit; and a control unit. The coarse delay line delays an external clock signal and outputs one or more pairs of first multi-phase clock signals and one or more pairs of second multi-phase clock signals. The coarse control compares the phase of the external clock signal with the phase of an inverted clock signal from among the one or more pairs of first multi-phase clock signals to provide a comparison result. The coarse control also controls the coarse delay line according to the comparison result. The clock interface selects a pair of clock signals having opposite phases, from among the one or more pairs of first multi-phase clock signals and the one or more pairs of second multi-phase clock signals. The clock interface also synthesizes the phase of a pair of the selected clock signals. The fine delay line finely delays the pair of the selected clock signals from the clock interface and outputs an internal clock signal synchronized with the external clock signal. The fine control unit compares the phase of the external clock signal with the phase of the internal clock signal and controls the fine delay line according to a comparison result. The control unit compares the phase of the external clock signal with that of the internal clock signal and controls the clock interface according to a digital comparison result.